Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and laptop personal computers. Recently, however, liquid crystal display devices provided with large-size screens and techniques for dealing with moving pictures have become more advanced, thus making it possible to realize not only mobile applications but also stay-at-home large-screen display devices and large-screen liquid crystal televisions. Liquid crystal display devices that rely upon active matrix drive and are capable of presenting a high-definition display are being utilized as these liquid crystal displays devices.
First, reference will be had to FIG. 17 to describe the typical configuration of a liquid crystal display device that employs active-matrix drive. The principal components connected to one pixel of a liquid crystal display unit are illustrated schematically by equivalent circuits in FIG. 17.
In general, a display unit 960 of an active-matrix liquid crystal display device comprises a semiconductor substrate on which transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are laid out in the form of a matrix (e.g., 1280×3 pixel columns×1024 pixels rows in the case of a color SXGA panel); an opposing substrate on the entire surface of which a single transparent electrode 967 is formed; and a liquid crystal material sealed between these two substrates arranged to oppose each other. The liquid crystal has capacitance and forms a capacitor 965 between the pixel electrode 964 and the electrode 967. Often an auxiliary capacitor 966 for assisting the capacitance of the liquid crystal is provided.
In this liquid crystal display device, the TFT 963, which has a switching function, is turned on and off under the control of a scanning signal. When the TFT 963 is on, a gray-scale level signal voltage that corresponds to a video data signal is applied to the pixel electrode 964, and the transmittance of the liquid crystal changes owing to a potential difference between each pixel electrode 964 and opposing-substrate electrode 967. This potential difference is held for a fixed period of time by the liquid-crystal capacitor 965 and auxiliary capacitor 966 even after the TFT 963 is turned off, as a result of which an image is displayed.
A data line 962 that sends a plurality of level voltages (gray-scale level signal voltages) applied to each pixel electrode 964 and a scanning line 961 that sends the scanning signal are wired on the semiconductor substrate in the form of a grid (the data lines are 1280×3 in number and the scanning lines are 1024 in number in the case of the above-mentioned color SXGA panel). The scanning line 961 and data line 962 constitute a large capacitive load owing to the capacitance produced at the intersection of these lines and capacitance, etc., of the liquid crystal sandwiched between the opposing-substrate electrodes.
It should be noted that the scanning signal is supplied to the scanning line 961 from a gate driver 970, and that the supply of gray-scale level signal voltage to each pixel electrode 964 is performed by a data driver 980 via the data line 962. Further, the gate driver 970 and data driver 980 are controlled by a display controller 950, a required clock CLK and control signals, etc., are supplied from the display controller 950, and video data is supplied to the data driver 980. At the present time, video data is principally digital data. A power-supply circuit 940 supplies driving power to the gate driver 970 and data driver 980.
Data rewriting of one screen is usually performed in one frame time interval (usually 1/60 seconds). Using each scan line, every pixel line (every line) is selected one by one, and within a selected period, the gray scale voltage is supplied through each data line.
Although the gate driver 970 need only supply at least a bi-level scanning signal, it is required that the data driver 980 drive the data lines by gray-scale level signal voltages of multiple levels that conform to the number of gray-scale levels. To this end, the data driver 980 has a digital-to-analog converter (DAC) comprising a decoder for converting video data to a gray-scale level signal voltage and an operational amplifier for amplifying the gray-scale level signal voltage and outputting the amplified signal to the data line 962.
Progress has been made in raising image quality (increasing the number of colors) in portable telephone terminals, laptop personal computers and liquid crystal TVs, etc. However, there is now growing demand for video data of six bits per each of the colors R, G, B (260,000 colors) and preferably 8-bit video data (16,800,000 colors) or higher.
For this reason, a data driver that outputs a gray-scale level signal voltage corresponding to multiple-bit video data is now required to output multiple gray-scale level voltages and, in addition, to produce highly accurate voltage outputs corresponding to tones. If the number of reference voltages generated in correspondence with multiple gray-scale level voltages is increased, then this causes an increase in the number of elements in a reference voltage generating circuit and in the number of reference voltage wires and in the number of switching transistors in the decoder circuit that selects reference voltages conforming to input video signals.
That is, progress in raising the number of gray-scale levels (represented by eight to ten bits or more) used invites an increase in the area of the decoding circuitry and an increase in the cost of the driver. The area of a multiple-bit DAC depends upon the decoder configuration.
A technique for reducing the number of reference voltages as well as the number of switching transistors in the decoder configuration by utilizing interpolation (an interpolation amplifier) is known in the art. A DAC having a configuration of the kind shown in FIG. 18 is disclosed in Patent Document 1 (Japanese Patent Kokai Publication No. JP2000-183747A) as related art of this type (see FIG. 1 in Patent Document 1). Referring to FIG. 18, a reference voltage generating circuit 118 produces reference voltages, which correspond to every other levels and are one-half plus one of the voltage levels which are output from the amplifier 117. In accordance with digital data, a selecting circuit (decoder) 116 selects two voltages out of reference voltages output by the reference voltage generating circuit 118. An interpolation amplifier 117 outputs a voltage obtained by interpolating the two voltages with a ratio of 1:1. The selecting circuit (decoder) 116 successively selects bits from the most significant bit (MSB: bit 5) toward the least significant bit (LSB: bit 0) of input digital data. The numbers of switches in the selecting circuit (decoder) 116 are 74, 270 and 1042 if the input digital data is composed of six bits, eight bits and 10 bits, respectively, as illustrated in FIG. 20A.
Further, a technique for reducing number of reference voltages and number of switching transistors by utilizing interpolation is disclosed in Patent Document 2 (Japanese Patent Kokai Publication No. JP2001-34234A). FIG. 19 is a diagram illustrating the configuration of a selecting circuit in a digital-to-analog converting circuit of a data driver disclosed in Patent Document 1 (see FIG. 10 in Patent Document 2). This arrangement uses an output amplifier circuit (interpolation amplifier) having two inputs (the amplifier is not shown). The interpolation amplifier receives OUT1 (Vn) and OUT2 (Vn+2) as inputs and outputs voltages obtained by internally dividing these two inputs at a ratio of 1:1. Tournament decoders (tournaments 1, 2, 3) are used as decoders for dividing an 8-bit input into six bits and two bits and decoding the 6-bit signal. With regard to 8-bit display data, input gray-scale levels (D0P, D0N, D1P, D1N, D2P, D2N, D3P, D3N, D4P, D4N, D5P, D5N) of six bits are divided into the following three blocks (A, B, C): Specifically, V(0), V(8), . . . V(0+8n), . . . V(248), V(256) are decoded by tournament 1; V(2), V(6), . . . V(2+4n), . . . V(250), V(254) are decoded by tournament 2; and V(4), V(4+8n), . . . V(252) are decoded by tournament 3.
A 6-bit-input first decoder (1st decoder) is constructed by tournament 1, tournament 2 and tournament 3. Outputs VA, VB and VC of the 1st decoder are input to a 2-bit (D6P, D6N, D7P and D7N) 2nd decoder) through a selecting circuit to which changeover signals D0N, D0P are applied, and two outputs OUT1(Vn) and OUT2(Vn+2) are obtained. The changeover signals D0N and D0P are applied to both the 1st decoder and the 2nd decoder. The selecting circuit selects one output from among the outputs VA, VB and VC of tournaments 1, 2 and 3, respectively, and inputs it to the 2nd decoder. The two outputs OUT1(Vn) and OUT2(Vn+2) of the 2nd decoder are input to the 2-input output amplifier circuit (interpolation amplifier) (not shown). This circuit approximately halves the number of reference voltages (gray-scale level voltages) using an interpolation amplifier. In accordance with the digital data, the decoder selectively outputs two voltages out of a number of reference voltages that is one-half plus one the number of outputs. Bits are selected from the least significant bit toward the most significant bit.
Patent Document 3 (Japanese Patent Kokai Publication No. JP2006-174180A) (see FIGS. 7 and 8 in Patent Document 3) discloses an arrangement of the kind shown in FIG. 21 in order to reduce the number of gray-scale level line even further. An interpolation amplifier outputs Vout=[V(T1)+V(T2)]/2. With reference to FIG. 21, means for selecting two voltages that are input to terminals T1 and T2 of a differential amplifier 400 includes a resistor string for outputting n analog voltages V1, V2, . . . , and Vn from respective taps; a first group composed of n switches S1a to Sna for selecting one voltage VS (where S represents an integer from 1 to n) from the taps; and a second group composed of n switches S1b to Snb for selecting one voltage VJ (where J represents an integer from 1 to n) from the taps. An Sth switch and a number Jth switch (Ssa and Sjb, respectively) of the first and second switch groups are turned on by an output of a decoder based on all of the bit signals (MSB+LSB) of the input data, whereby it is possible to select any combination (VS, VJ) of tap voltages, including duplicate values as voltages (VT1, VT2) of the terminals T1, T2. The differential amplifier 400 includes a first differential pair (101, 102); a second differential pair (103, 104); a current mirror circuit (111, 112) connected to the output pairs of the first and second differential pairs and forming a common active load with respect to the first and second differential pairs; an amplifier stage 6, to which output signals of the current mirror circuits (111, 112) are input, for outputting a voltage Vout to an output terminal 3; and current control transistors 126, 127 for supplying currents (11, 12) that flow into the first and second differential pairs. A control terminal (gate) of transistor 101 of the first differential pair is connected to an input terminal T1, a control terminal (gate) of transistor 103 of the second differential pair is connected to an input terminal T2, and control terminals of transistors 102, 104 of the first and second differential pairs are both connected to the output terminal 3. Output voltage Vout is fed back to the input side. Further, let VT1 and VT2 represent the terminal voltages of the input terminals T1 and T2, respectively. Bias voltages VB11, VB12 are supplied to the control terminals (gates) of the current control transistors 126, 127, respectively.
FIG. 21 illustrates a typical configuration of the current mirror circuit (111, 112) connected between output pairs of the respective first differential pair (101, 102) and second differential pair (103, 104) and a high-potential power supply VDD. Specifically, the current mirror circuit (111, 112) includes transistors 111 and 112. A source of the transistor 112 is connected to the high-potential power supply VDD, and a drain and a gate of the transistor 112 are connected in a diode configuration and form an input terminal of the current mirror circuit. A source and a gate of the transistor 111 are connected to the power supply VDD and to the gate of the transistor 112, respectively, and a drain of the transistor 111 forms an output terminal of the current mirror circuit. An input terminal of the current mirror circuit (the drain of the transistor 112) is connected in common with the drains of the transistors 102 and 104, and an output terminal of the current mirror circuit (the drain of the transistor 111) is connected in common with the drains of the transistors 101 and 103 and forms an output terminal 4 of the differential stage. The output terminal 4 is connected to the input terminal of the amplifying stage 6.
The differential amplifier 400, in which the first differential pair (101,102) and the second differential pair (103,104) are composed by transistors having the same characteristics, when the current ratio of currents I1 and I2 which respectively flows through the first differential pair (101,102) and the second differential pair (103,104) assumes an equal value, that is I1=I2, is capable of outputting a voltage obtained by internally dividing (or interpolating) the voltages VT1 and VT2 at the input terminals T1 and T2 with an internal ratio 1:1.
FIG. 22 shows an example of a method of selecting the two input voltages applied to the terminals T1 and T2 of the differential amplifier 400 of FIG. 21. FIG. 22 shows, in a tabulated form, nine voltages of equally spaced levels, four voltages A, B, C, D different from one another and output from respective taps of the resistor string of FIG. 21, and combinations of two voltages that are input to the terminals T1 and T2. It does not matter which one of the voltages in a combination of the two voltages is output to which one of the terminals T1 and T2. The number of voltages applied to the terminals T1 and T2 is only four, which is less than one-half the number of output voltages of the nine levels. However, the two voltages that are input can be combined such that when the voltage A, for example, is selectively input to one of the two terminals (T1, T2), any of the four voltages A, B, C and D can be applied to the other terminal. Thus, there are a total of ten combinations of two out of four voltages, thereby making a 9-level linear output possible. The first to fourth reference voltages (A, B, C, D) having voltage values that differ from one another are input to the differential amplifier 400 (the four reference voltages A, B, C, D are set to first, third, seventh and ninth voltage levels from among the output voltages of the nine levels). Any pair among the following pairs is supplied to the terminals T1 and T2 of the differential amplifier 400:
(1) the pair of first voltages (A,A), output level=(A+A)/2;
(2) the first and second voltages (A,B), output level=(A+B)/2;
(3) the pair of second voltages (B,B), output level=(B+B)/2;
(4) the first and third voltages (A,C), output level=(A+C)/2;
(5) the second and third voltages (B,C), output level=(B+C)/2, or the first and fourth voltages (A,D), output level=(A+D)/2;
(6) the second and fourth voltages (B,D), output level=(B+D)/2;
(7) the pair of third voltages (C,C), output level=(C+C)/2;
(8) the third and fourth voltages (C,D), output level=(C+D)/2; and
(9) the pair of fourth voltages (D,D), output level=(D+D)/2.
A maximum of nine voltage levels that differ from one another are output from the output terminal of the differential amplifier 400. Two combinations of two voltages applied to the terminals (T1, T2) for implementing the output of the fifth level are possible, namely the combination of voltages B and C and the combination of voltages A and D.
In FIG. 22, the first to eighth levels among the output voltages of the nine levels can be made to correspond to data (0,0,0) to (1,1,1) with respect to 3-bit digital data (D2,D1,D0).